Comparing the DV-414 word clock (top) and left channel data (bottom): 
<br>
<img src="images/wclk-ldata.jpg">
<br>

to the I2S spec:
<br>
<img src="images/i2se-timing.gif">
<br>

it's clear that the word clock needs to be inverted
since I2S (e) seems to clock left on the falling word clock,
while the DV-414 clocks left on the rising word clock.
<p>
The conventional way to invert a signal would be use an inverter
like the 74HCT04.
A 74HCT04 has a typical propagation delay of 6 nS at 5 VCC
so some gates from it could be useable for inversion and/or delay.
But how about this as an alternative:
the Motorola driver chip 
<a href="http://www.onsemi.com/pub/Collateral/mc10h352rev6.pdf">MC10H352</a>
has inverting and non inverting output to drive the line
balanced.  How about simply switching the inverting and non-inverting
lines somewhere between the chip and the output connector?
I've confirmed with DAC-3 designer Peter Schut that this approach should work.
<p>
(Note that the corresponding Motorola PECL receiver is the
<a href="http://www.onsemi.com/pub/Collateral/mc10h350rev7.pdf">MC10H350</a>.)
<p>

Combining the 44.1 k waveforms (word clock, bit clock, master clock, 
from top to bottom):

<br>
<img src="images/44-combined.jpg">
<br>

to the timing requirements of I2Se:

<br>
<img src="images/i2se-timing2.gif">
<br>
Other than the word clock,
the phasing of the DV-414 signals looks good.
Like I2S, they clock on their falling edges
(notice how the bit clock <em>falls</em> just as the word clock rises).
<p>

One of the I2Se requirements is that the word and bit clocks
need to be delayed 1-20 nS relative to the rising master clock.
The signals above appear to just meet that spec.
<p>

However for 96 x 24 the timing becomes more critical and
the window narrows to 10 nS.
Combining the 96 kHz clocks below, they do seem to meet the 1-10 nS window.

<br>
<img src="images/96-combined.jpg">
<br>
(As in the combined 44k waveforms above, the 96k combination here
has word clock on top, bit clock middle, and master clock bottom.)
<p>

One other issue is that I2S data is left-justified (with a 1 bit clock
delay from the word clock) whereas the DV-414 is right-justified.
(The DV-414 signal format appears to follow the Sony/Burr-Brown standard.)
If this is critical to I2S, there may be no simple way to get I2Se outputs
from the DV-414.  
You could put a CS 8414 reciever and associated PLL into the DVD player,
but that complexity belongs better on the receiver side in the external DAC.
The best approach would probably be to add the second, 
high precision PLL to the receiver in the DAC, 
as Peter is doing for a future revision of the DAC-3 digital board.